OCTOBER 25, 2026
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SK Hynix Plans to Pack Over 100 Custom Processors into Future SSD Controllers for PCIe 8.0 Era

SK Hynix Plans to Pack Over 100 Custom Processors into Future SSD Controllers for PCIe 8.0 Era

South Korea’s memory producer SK Hynix said it will embed upwards of a hundred specialized processing chips within the controllers of its upcoming solid‑state drives, a step intended to ready the market for the forthcoming PCIe 8.0 specification and the rise of ultra‑fast flash storage.

These bespoke chips, called H‑TPUs, are built to perform particular storage functions and draw merely about 2.5 percent of the energy a standard CPU core would need for an equivalent job. Since each H‑TPU takes up roughly four percent of the silicon footprint of a generic core, many can be integrated onto one controller without enlarging the die.

With this tightly packed collection of dedicated processors spread throughout the controller, SK Hynix anticipates shifting a substantial portion of data‑transfer and error‑correction duties away from the host CPU. The efficiency improvements are likely to benefit data‑center servers and enterprise platforms that must handle terabytes per second once PCIe 8.0 doubles the throughput of the previous generation.

The move coincides with Samsung, SK Hynix’s main competitor in NAND, accelerating its own high‑end SSD lineups. Analysts see the push to integrate dedicated logic as an inevitable progression, as flash densities rise while power envelopes stay constrained. Performing operations inside the SSD controller also cuts latency, a vital requirement for uses like AI inference and real‑time analytics.

SK Hynix did not reveal an exact launch date for the initial SSDs equipped with H‑TPU‑laden controllers, yet it confirmed that development is in progress and the solution should be available for the PCIe 8.0 debut slated for later this decade. Should it prove effective, the strategy may establish a fresh standard for SSD design, urging rivals to follow suit with comparable multi‑processor architectures to remain viable in a market driven by speed, efficiency, and ever‑growing flash capacities.

Source: TechRadar
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